This disclosure relates to circuit packaging, and more particularly, to a stacked die package for reducing die packaging cost, a system including the same, and a method of manufacturing the same.
A semiconductor wafer includes several hundred or thousand chips on which the same electrical circuit is printed. The chips cannot communicate with external devices by themselves. Accordingly, electrical wiring is connected to a chip to enable the chip to communicate with external devices and they are hermetically packaged in a semiconductor packaging process so as to endure external impact such as physical impact or chemical impact. The semiconductor packaging process, also known as a die packaging process, is often one of the last steps in the semiconductor manufacturing processes.
When a plurality of dies are stacked on a package substrate using wire bonding, each of the dies includes a redistribution layer (RDL) which connects a center pad with an edge pad. When the distance between the center pad and the edge pad increases, the capacitance and the resistance of the dies also increase. In addition, since an RDL process is added, packaging cost increases.
When dies are stacked on a package substrate using a through-silicon via (TSV), a process of forming the TSV in the dies may be required, resulting in an increase in the packaging cost.